Job openings for asic design verification engineer in ahmedabad bangalore mumbai

As a Design Verification Engineer, you will be responsible for verifying complex IC designs through simulation and other verification methodologies. You will work closely with design, architecture, and validation teams to ensure the functional correctness and quality of our ICs, meeting stringent performance and reliability requirements.
Responsibilities:
Develop and execute verification plans for digital IC designs
Write and debug SystemVerilog/UVM testbenches and test scenarios
Perform functional verification using simulation tools (e.g., Questa, VCS)
Conduct RTL linting, code coverage analysis, and assertion-based verification
Collaborate with design and architecture teams to understand design specifications and requirements
Define and implement verification methodologies and strategies
Analyze and debug simulation failures, and work with design teams to resolve issues
Participate in design reviews, providing verification perspective and feedback
Generate and maintain verification documentation and reports

Qualifications:
Bachelor��s or Master��s degree in Electrical Engineering, Computer Engineering, or related field
3-8 years of experience in ASIC or FPGA design verification
Strong proficiency in SystemVerilog and experience with UVM methodology
Hands-on experience with simulation tools (e.g., Questa, VCS)
Familiarity with code coverage analysis, functional coverage, and assertion-based verification
Knowledge of scripting languages (e.g., Perl, Python, TCL) for automation
Understanding of digital design fundamentals and computer architecture
Excellent problem-solving and analytical skills
Strong communication and interpersonal skills, with the ability to work effectively in a team environment
Experience with formal verification tools and methodologies
Knowledge of low-power design techniques and methodologies
Familiarity with industry-standard protocols (e.g., PCIe, DDR, Ethernet)
Background in hardware emulation and FPGA prototyping, post-silicon validation