Ahmedabad, Bangalore, Mumbai, Pune, Hyderabad, Delhi
As a Design for Testability Engineer, you will play a critical role in ensuring the testability and manufacturability of our IC designs. You will collaborate closely with design, verification, and manufacturing teams to implement robust DFT strategies and methodologies
Responsibilities:
Develop DFT specifications and strategies for complex IC designs from early concept to tape-out
Implement scan insertion, ATPG (Automatic Test Pattern Generation), and MBIST (Memory Built-In Self-Test) solutions
Collaborate with RTL designers to ensure DFT requirements are met without compromising design goals
Perform DFT simulations and analysis to verify functionality and test coverage
Generate test vectors and patterns for manufacturing test programs
Optimize DFT architectures to achieve high fault coverage and improve test efficiency
Work with external test vendors and manufacturing partners to validate test patterns and ensure seamless test program integration
Participate in DFT reviews and provide recommendations for design improvements
Document DFT specifications, methodologies, and test plans
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
Proven experience in DFT implementation for complex IC designs, preferably 3+ years
Proficiency in industry-standard DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Encounter Test
Strong understanding of scan-based testing, ATPG algorithms, and memory test methodologies
Familiarity with BIST (Built-In Self-Test) techniques and IEEE 1149.x (JTAG) standards
Experience with RTL design, verification flows, and design closure processes
Knowledge of semiconductor manufacturing processes and test equipment
Strong communication and interpersonal skills, with the ability to work effectively in a team environment
Experience with DFT for advanced process nodes (e.g.,7nm, 5nm)
Knowledge of DFT for analog and mixed signal designs
Familiarity with scripting languages
Experience | 5 - 10 Years |
Salary | 20 Lac To 30 Lac P.A. |
Industry | Architecture / Interior Design |
Qualification | B.E, B.Tech, M.Tech |
Key Skills | Dft Engineer Atpg DFT Simulation IC Design Cadence Allegro JTAG ISO Documentation |
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